- Google is in talks with Marvell Technology to co-develop two new custom chips: a memory processing unit (MPU) designed to run alongside its TPUs, and a dedicated inference TPU.
- Google plans to produce nearly two million of the memory processing units, with chip designs expected to be finalized by 2027.
- The partnership is partly driven by a desire to reduce dependence on Broadcom, which charges high per-unit licensing fees for each TPU produced.
- Broadcom signed a new supply contract with Google through 2031 in early April 2026, meaning both relationships will coexist for the foreseeable future.
What Happened
Google is in talks with chip designer Marvell Technology to develop two new specialized chips for its data centers, according to reporting by The Decoder, which cited a report from The Information based on two people familiar with the matter. The discussions were reported in April 2026 and mark a notable expansion of Google’s custom silicon strategy beyond its existing relationship with Broadcom.
One chip is a memory processing unit intended to run alongside Google’s in-house Tensor Processing Units (TPUs), distributing AI workloads by separating compute-intensive tasks from memory-intensive ones. The second is a new TPU variant built specifically for inference—the process of running a trained model against live inputs rather than training the model itself.
Why It Matters
Google has developed its TPU line internally since 2016, but has relied on third-party chip designers—primarily Broadcom—to manufacture and produce those designs at scale. Broadcom charges per-unit fees that, at the volumes Google operates, represent a substantial ongoing cost. Diversifying to Marvell gives Google a second design partner and potential leverage over chip economics.
The move also reflects a broader industry trend: hyperscalers including Amazon (Trainium, Inferentia), Microsoft (Maia), and Meta (MTIA) have all accelerated custom silicon programs to reduce their exposure to Nvidia’s pricing and supply constraints. Google’s decision to commission a chip purpose-built for inference aligns with a shift in AI compute economics, where inference workloads now account for a growing share of total data center spend.
Technical Details
The memory processing unit is designed to work in tandem with Google’s existing TPUs rather than replace them. The architecture splits AI task execution based on whether a given operation is bottlenecked by compute throughput or memory bandwidth—a distinction that becomes significant at large model scales where moving data between compute units and memory is often the limiting factor.
Google plans to produce nearly two million units of the memory processing chip, with the design phase expected to conclude by 2027. Marvell is a credible partner for this work: the company previously designed the first custom inference chip for the AI inference startup Groq, whose founder Jonathan Ross is one of Google’s original TPU engineers. Nvidia acquired a license to Groq’s LPU (Language Processing Unit) architecture in December 2025 for $20 billion and subsequently announced the Groq 3 LPU and Groq 3 LPX rack system at its GTC 2026 conference.
The inference-specific TPU is a separate development from the MPU. Dedicated inference accelerators typically optimize for lower latency and higher throughput on fixed model weights, trading off the flexibility needed during training for better performance-per-watt at serving time.
Who’s Affected
Broadcom remains Google’s primary TPU production partner: the two companies signed a new supply contract extending through 2031 in early April 2026, indicating the Marvell relationship is additive rather than a direct substitution. Broadcom investors and analysts will be watching whether Google’s volume commitments to Broadcom shift over the contract period as Marvell chips come online.
Marvell stands to gain a significant new hyperscaler customer and, given the reported production target of nearly two million units, a substantial volume contract. For Nvidia, the development is a signal that Google is intensifying its effort to build out inference infrastructure that bypasses Nvidia’s GPU-centric stack entirely.
What’s Next
The chip designs are expected to be finalized sometime in 2027, after which production ramp and data center deployment would follow on a timeline that has not been publicly disclosed. Google has not confirmed the talks or provided specifications for either chip.
The Information’s sourcing is limited to two unnamed individuals, and neither Google nor Marvell has issued official statements. Further detail on chip specifications, production contracts, and deployment timelines would likely emerge only after design finalization or a formal announcement from either company.
